The present invention relates to test circuitry for integrated circuits and in particular to an improved wrapper cell permitting the injection and extraction of signals into and out of an integrated circuit for testing of the integrated circuit.
Complex integrated circuits must be individually tested as part of the manufacturing process. This testing process applies a predetermined test sequence to the inputs of the circuit and monitors the outputs of the circuit to see that they conform to the expected outputs for a properly functioning circuit.
System on a chip (SoC) integrated circuits, and other complex integrated circuits, combine multiple functional elements on a single substrate. For example, such systems can combine digital, analog, mixed signal, and radiofrequency functional elements on a single substrate to produce a more complex device such as microcontroller or cell phone. Commonly, an SoC design will provide for logic functional elements with embedded non-logic blocks of functional elements including memories, custom-designed coprocessors, analog to digital converters, phase locked loops, FPGAs and the like.
Often these functional elements are designed by different commercial entities and/or are proprietary, representing in functional element “black boxes” in which the user must rely on a test sequence unique to that functional element and developed by others. Or, for reasons of managing the complexity of the testing process, it may be necessary to test the combined functional elements separately.
In either case, it is known to embed circuitry within the integrated circuit allowing isolated testing of the different internal functional elements. This circuitry is typically termed a “wrapper” and comprises, in part, a series of “wrapper cells” which can be placed at points of interconnection between functional elements to allow the monitoring of signals at the those interconnections and the injection of test signals at those interconnections.
Often wrapper cells may be arranged so that test data (both input and output data) can be shifted into and out of the cells in the manner of a shift register along a limited number of I/O lines. This approach reduces the total pin count of the integrated circuit package. One standard for making such wrapper cells is IEEE standard 1500 which will be described in more detail below.
Commonly, functional elements of complex integrated circuit are arranged in a hierarchical or parent-child fashion. Such functional elements may be termed “parent” and “child” cores the term “core” referring to any functional element not necessarily a processor. A child core may be a parent of other child cores.
Conventional wrapper cells per IEEE standard 1500 do not permit simultaneous testing of the parent and child core. This was recognized in the paper: Goel S K, Marinissen E J, Sehgal A, Chakrabarty K (2009) Testing of SoC's with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling IEEE Trans Computers 58(3):409-423. This paper proposed a new wrapper cell comprising two memory elements (flip-flops) and three to four multiplexers in contrast to the IEEE standard 1500 wrapper core having two multiplexers and one memory element.